Parallel-Array Implementations of a Non-Restoring Square Root Algorithm

نویسندگان

  • Yamin Li
  • Wanming Chu
چکیده

In this paper, we present a parallel-array implementation of a new non-restoring square root algorithm (PASQRT). The carry-save adder (CSA) is used in the parallel array. The PASQRT has several features unlike other implementations. First, it does not use redundant representation for square root result. Second, each iteration generates an exact resulting value. Next, it does not require any conversion on the inputs of the CSA. And last, a precise remainder can be obtained immediately. Furthermore, we present an improved version — a root-select parallel-array implementation (RS-PASQRT) for fast result value generation. The RS-PASQRT is capable of achieving up to about 150% speedup ratio over the PASQRT. The simplicity of the implementations indicates that the proposed approach is an alternative to consider when designing a fully pipelined square root unit.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Cost/Performance Tradeoff of n-Select Square Root Implementations

Hardware square-root units require large numbers of gates even for iterative implementations. In this paper, we present four low-cost high-performance fullypipelined n-select implementations (nS-Root) based on a non-restoring-remainder square root algorithm. The nSRoot uses a parallel array of carry-save adders (CSAs). For a square root bit calculation, a CSA is used once. This means that the c...

متن کامل

A New Non-Restoring Square Root Algorithm and Its VLSI Implementations

In this paper, we present a new non-restoring square root algorithm that is very efficient to implement. The new algorithm presented here has the following features unlike other square root algorithms. First, the focus of the “nonrestoring” is on the “partial remainder”, not on “each bit of the square root”, with each iteration. Second, it only requires one traditional adder/subtractor in each ...

متن کامل

Implementation of single precision floating point square root on FPGAs

Square root operation is hard to implement on FPGAs because of the complexity of the algorithms. In this paper, we present a non-restoring square root algorithm and two very simple single precision floating point square root implementations based on the algorithm on FPGAs. One is low-cost iterative implementation that uses a traditional adder/subtractor. The operation latency is 25 clock cycles...

متن کامل

A 32-Bit Signed/Unsigned Fixed Point Non-Restoring Square-Root Operation Using VHDL

After analyzing the advantages and disadvantages of all the general algorithms adopted in designing square root on FPGA chips with pipeline technology, a proposed algorithm based on digit by digit calculation method is discussed. The algorithm is realized on the ModelSim SE 6.3f development platform with VHDL language and the simulation results show that it is characterized by occupying less re...

متن کامل

A New Non-Restoring Square Root Algorithm and its VLSI Implementation

In this paper, we present a new non-restoring square root algorithm that is very efficient to implement. The new algorithm presented here has the following features unlike other square root algorithms. First, the focus of the “nonrestoring” is on the “partial remainder”, not on “each bit of the square root”, with each iteration. Second, it only requires one traditional adder/subtractor in each ...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 1997